1. Field of the Invention
The present invention relates to a clock synchronizing system and a synchronizing method, in particular to a receiver-side clock synchronizing system and a synchronizing method. In a transmission scheme, the count information item obtained by counting the clock is intermittently multiplexed with the coded information data encoded by sampling of information item such as image or voice in accordance with a sampling clock and transmitted. And, the count information item is received by the receiver.
2. Description of the Related Art
One example of this type of conventional clock synchronizing system is shown in the block diagram of FIG. 3. FIG. 3A shows a transmitter side block, and coded data 101 sampled in accordance with the system clock 102 forms one input of the multiplex section 8. On the other hand, a counter 9 for counting the relevant system clock 102 is provided and this count output 103 forms the other input of the multiplex section 8 as system clock reference information item SCRn (employed as clock recovery signal on the receiver side).
Incidentally, "n" in SCRn represents the time-series numeral (number) of SCR to be intermittently multiplexed with coded data 101 in the multiplex section 8 and on letting n=1 be the first SCR, n will take an integer of 1 or greater.
In the multiplex section 8, coded data 101 and SCRn 103 which is the counter count information item are multiplexed, and the SCRn 103 is inserted into a predetermined place of the header part of a send frame and transmitted as multiplexed data 104.
On referring to FIG. 3B showing the receiver block side, the received multiplexed data 104 are supplied to the separating section 1 and separated into coded data 105 and SCRn 106, respectively. The SCRn 106 forms one input of a differential 2, to the other input is supplied the latch output of a FF (flip-flop) 7 for data latch and the difference between both inputs is output from the differential 2.
Because of being a digital signal, this difference value is converted into an analog signal by a D/A convertor 3 and becomes the control voltage for a VCXO (voltage control type oscillator) 5 via an LPF (low pass filter) 4 for smoothing this analog signal. This VCXO5 is arranged to oscillate at the same frequency as the system clock 102 and this oscillation output is used as a sampled clock 109 on the receiver side.
This oscillation output 109 is inputted to a counter 6 and successively counted. As the initial value of this counter 6, the initial value 108 from the differential 2 is loaded. This count output SCCn is transferred to the FF7 as a system clock counter value (SCC) and latched for each timing of the SCR latch pulse 107 from the separating section 1 and the latch output becomes the other input of the differential 2.
The first-time received SCR1 is loaded to the counter 6 as an initial value. The SCRn arriving at the second time and the subsequent times respectively are compared with the count value SCC2 of the counter 6 in the differential 2 and corresponding to the differential 2, the VCXO 5 is controlled, so that the received SCR2 and the SCC2 are so controlled as to coincide with each other. According to such a control, the clock of the oscillation output of the VCXO5 whose phase coincides with that of the sampled clock on the sender side ends is being obtained on the receiver side, so that the clock recovery on the receiver side is possible.
Incidentally, such a clock recovery (synchronization) scheme is shown as the ANNEX (appendix) of the standard document ISO/IEC 13818-1.
According to such a conventional prior art, in the clock recovery (synchronization) scheme on the receiver side, the differential of the clock recovery information item SCRn with a count value of a counter for counting the autorunning clock of the voltage controllable VCXO is taken and in accordance with the difference, this VCXO is controlled, thereby enabling update of a control voltage to be performed regularly.
However, by factors such as restrictions due to a format of the transmission scheme and a rise in the transmission efficiency of coded data of an image, the delivery interval of SCRn, the clock recovery information item, may become variable in some cases. If a local frequency fluctuation takes place on the time axis like this, a conventional scheme cannot follow such a frequency fluctuation and consequently has a disadvantage that the clock recovery processing (synchronous processing) delays.